The present invention relates to a manufacturing method for a semiconductor device.
The market not only demands sophistication for portable electronics devices, such as mobile telephones, PDAs (personal digital assistants), DVCs (digital video cameras), and DSCs (digital still cameras), but also demands compact and lightweight products. Highly integrated system LSI (large scale integration) technology is one solution to meet such market demands.
One example for realizing a highly integrated system LSI is a high-frequency bipolar transistor. To enable a high-frequency bipolar transistor to have higher performance, a heterojunction bipolar transistor including a base layer fabricated with a silicon-germanium (SiGe) alloy has been proposed. FIGS. 1 and 2 show the structure of a conventional heterojunction bipolar transistor including a SiGe alloy base layer described in Japanese Laid-Open Patent Publication No. 4-179235.
In FIG. 1, an n−-type layer (epitaxial layer) 102, which functions as a collector layer, is epitaxially grown on a p−-type silicon substrate (not shown) with an N+-type collector embedment layer 101 arranged in between. The n−-type layer 102 is etched to remove unnecessary portions and leave only the necessary portions, such as portions corresponding to a collector layer and a collector lead layer. A trench is formed in an isolation region. A polycrystalline silicon film 104 is embedded in the trench by means of an oxide film 103. After the collector formation and the isolation region embedment, the surface of the silicon substrate is planarized using an oxide film (buried oxide film) 105. A base and an emitter are further epitaxially grown on the surface of the structure. More specifically, a p-type SiGe layer (SiGe alloy layer) 106, which functions as an internal base layer, is epitaxially grown on the surface of the structure. An n-type silicon layer 107, which functions as an emitter layer, and an N+-type silicon layer 108, which functions as an emitter-contact layer (emitter electrode), are epitaxially grown on the p-type SiGe layer 106 sequentially in the stated order. The N+-type silicon layer 108 and the n-type silicon layer 107 are etched using an oxide film 109 as a mask to remove unnecessary portions and leave necessary portions such as portions corresponding to an emitter. An oxide film (side wall film) 110 and the oxide film 109 are used as a mask, and a portion of the remaining p-type SiGe layer 106 surrounding the region that functions as an internal base layer is etched to a predetermined depth. A p+-type SiGe layer 111, which functions as an external base layer, is formed through selective epitaxial growth on the portion surrounding the p-type SiGe layer 106.
In the conventional structure of the heterojunction bipolar transistor including the SiGe base layer shown in FIG. 2, the n-type silicon layer 107 functioning as an emitter layer has a reverse T.-shaped cross-section, and a contact surface 150 between the emitter layer 107 and the emitter electrode 108 is located above a lower surface 160 of the side wall film 110. As a result, an emitter-base junction portion is formed below a relatively narrow projection of the emitter layer 107. The width of the emitter-base junction portion, that is, the width We2 of the emitter layer is greater than the width We1 of the N+-type silicon layer (emitter electrode) 108.